The present invention concerns an integrated circuit comprising a standard cell, an application cell and a test cell designed in particular to monitor communication signals between the previous two cells.
Modern electronic devices, and especially those which process digital signals, often comprise a programmable unit such as a microprocessor associated with a program memory and an application circuit combining peripheral circuits of the programmable unit and logic circuits specific to the functions that these devices implement. They are routinely mounted on an electronic circuit board on which the programmable unit and its memory are two standard components whereas the application circuit is usually an application-specific integrated circuit. The connections between these three components are therefore all visible on the circuit board and test or emulation equipment can therefore access them during the various test and debugging phases of the development of such devices.
Technological advances in the field of microelectronics now make it feasible to integrate in a single component the various devices that were previously mounted on a circuit board of this kind. The programmable unit is usually a standard cell defined by the manufacturer whereas the application circuit is specified by the component designer. The program memory is also usually a standard subsystem which in this disclosure will be arbitrarily combined with the application circuit to constitute what is referred to hereinafter as the "application cell". With this mode of implementation the only device connections accessible are the component leads which are reduced in number as compared to a printed circuit board implementation because most of the communication links between the standard cell and the application cell are not connected to pins. It is not desirable to increase significantly the number of pins as this increases the size and the cost of the component. It may even be ruled out by virtue of the technology employed. As a result, it is impossible to use known test and emulation methods on such components. The successive stages which previously consisted in debugging the application cell, developing the programming memory software, debugging this software and finally debugging the device as a whole can no longer be dissociated.
It is possible to use a computer-aided design tool to simulate the interaction between the standard cell and the application cell. In this way it is possible to verify mainly the operation of the communication links between the two cells. However, such simulations are time-consuming and costly given the computing power of the simulation tools. Component development and debugging times become incompatible with industrial constraints.
It is also possible to obtain from some manufacturers a component kit in which the programmable unit and the application cell are separate devices. During the test phase, the device is implemented as a mock-up in which the connections between the two components are accessible and so can be treated in a similar way to connections on electronic circuit boards. In this case the mock-up development cost is additional to the cost of the fully integrated component. Also, the performance of the mock-up device, and in particular its execution speed, are significantly degraded in comparison with what can be expected of the same device in its integrated version. It is therefore impossible to reproduce this version in all respects. The problem of limited speed is particularly accentuated if the programmable unit is a signal processor. The "boundary scan" test and emulation technique described in particular in IEEE (Institute of Electrical and Electronic Engineers) standard 1149.1 is used in the case of a fully integrated component. In this technique, a test cell is disposed between the standard cell and the application cell. It comprises, for each communication link, a scanning unit provided with a unit memory, these unit memories being interconnected to form a shift register connected to pins of the component. It is therefore possible, by adding a limited number of input/output pins, to record and to modify the communication signals carried by the communication links. This technique makes is possible to debug the application cell. It has the drawback of disrupting the communication links during movement of the information stored in the shift register because of the connections between these components.
When the test and emulation procedure is carried out, it is necessary to be able to command the test cell in response to a particular state of the various input/output signals of the standard cell.
The American company MOTOROLA has drawn up for the DSP 96000 signal processor an emulation technique it calls "on-chip emulation". In this technique the signal processor is a standard cell to which is added a serial interface enabling execution to be resumed after a break point and loading of an instruction by means of a set of registers and address comparators connected to the buses of the cell adapted to produce break points. The status of these buses can be read via the serial interface. This solution does not cover the case of a circuit comprising also an application cell, but only the cases where the standard cell is an "open" processor, meaning a processor whose instruction bus is accessible, or where the program memory is a RAM type rewritable memory. It does not make it possible to read the information present on the buses independently of the operation of the standard cell.
Patent application EP-0 358 376 discloses a test cell comprising a shift register in which stored information can circulate without disrupting the communication links. This test cell can also be commanded in response to the status of the standard cell input/output signals.
However, when the integrated circuit has been fabricated by the manufacturer, an error may remain in the program memory, which is often a read only memory (ROM). Any such error in the memory cannot be corrected. To alleviate this drawback, some manufacturers add to the circuit an additional rewritable memory such as an EPROM or EEPROM, for example. This additional memory uses specific technology which can limit the performance of the circuit in terms of processing speed and which is not necessarily compatible with the technology of the remainder of the circuit.